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EPSRC CDT in Next Generation Computational Modelling

NGCM Summer Academy: Programming the Intel Xeon Phi

Intel Phi inside.. `source <>`__

Students and academics received a two day training course on programming the Intel Xeon Phi to kick off this week's events at the first annual NGCM Summer Academy. Adrian Jackson of the Edinburgh Parallel Computing Center (EPCC) delivered the material, which is available on the Archer website.

With the diminishing performance advances of individual processing units, many-core devices with like the Xeon Phi show potential for next generation computing. Although Graphics Processor Units (GPU's) have also seen great usage in this area in recent years, the Xeon Phi consisting of 60 compute cores has advantages of code portability and represents a hybrid between standard processors and GPU's.

Participants of the course were given access to the 24 Xeon Phi nodes of the Iridis Compute Cluster to practice with the provided exercises in using the Xeon Phi, and code optimisation techniques to exploit its performance.

Intel Xeon Phi Processors `source <>`__

Intel Xeon Phi Processors source